Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in / Register
Toggle navigation
T
Tenjin
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Charts
Packages
Packages
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
Nawasan Wisitsingkhon
Tenjin
Commits
36bf05c2
Commit
36bf05c2
authored
Jun 24, 2024
by
Nawasan Wisitsingkhon
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
match fields marshal
parent
b2b05232
Expand all
Show whitespace changes
Inline
Side-by-side
Showing
2 changed files
with
10 additions
and
0 deletions
+10
-0
mac_address.rs
src/etherparser/net/mac_address.rs
+10
-0
match_fields.rs
src/openflow/ofp13/events/flow_mod/match_fields.rs
+0
-0
No files found.
src/etherparser/net/mac_address.rs
View file @
36bf05c2
use
byteorder
::
WriteBytesExt
;
pub
struct
MacAddr
{
pub
struct
MacAddr
{
mac
:
[
u8
;
6
],
mac
:
[
u8
;
6
],
}
}
...
@@ -8,6 +10,14 @@ impl MacAddr {
...
@@ -8,6 +10,14 @@ impl MacAddr {
}
}
}
}
impl
MacAddr
{
pub
fn
marshal
(
&
self
,
bytes
:
&
mut
Vec
<
u8
>
)
{
for
m
in
self
.mac
.iter
()
{
bytes
.write_u8
(
*
m
);
}
}
}
impl
From
<
MacAddr
>
for
u64
{
impl
From
<
MacAddr
>
for
u64
{
fn
from
(
value
:
MacAddr
)
->
Self
{
fn
from
(
value
:
MacAddr
)
->
Self
{
let
mut
byte
:
u64
=
0
;
let
mut
byte
:
u64
=
0
;
...
...
src/openflow/ofp13/events/flow_mod/match_fields.rs
View file @
36bf05c2
This diff is collapsed.
Click to expand it.
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment